annotate redelacSticsSimulator.R @ 5:fa8e742b197b draft

"planemo upload for repository https://forgemia.inra.fr/redelac/redelac-toolbox/-/tree/e5d2c43e9169b2209fd3267e9eb09a9593f55436/tools/REDELACSticsSimulator commit e5d2c43e9169b2209fd3267e9eb09a9593f55436-dirty"
author siwaa
date Mon, 21 Aug 2023 15:47:50 +0000
parents 70ae7516e925
children 41f652e6616f
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
2
ea8e91473dc8 "planemo upload for repository https://forgemia.inra.fr/redelac/redelac-toolbox/-/tree/4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4/tools/REDELACSticsSimulator commit 4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4-dirty"
siwaa
parents:
diff changeset
1 library(SticsRFiles)
ea8e91473dc8 "planemo upload for repository https://forgemia.inra.fr/redelac/redelac-toolbox/-/tree/4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4/tools/REDELACSticsSimulator commit 4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4-dirty"
siwaa
parents:
diff changeset
2 library(SticsOnR)
ea8e91473dc8 "planemo upload for repository https://forgemia.inra.fr/redelac/redelac-toolbox/-/tree/4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4/tools/REDELACSticsSimulator commit 4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4-dirty"
siwaa
parents:
diff changeset
3 library(parallel)
ea8e91473dc8 "planemo upload for repository https://forgemia.inra.fr/redelac/redelac-toolbox/-/tree/4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4/tools/REDELACSticsSimulator commit 4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4-dirty"
siwaa
parents:
diff changeset
4 library(doParallel)
ea8e91473dc8 "planemo upload for repository https://forgemia.inra.fr/redelac/redelac-toolbox/-/tree/4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4/tools/REDELACSticsSimulator commit 4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4-dirty"
siwaa
parents:
diff changeset
5 library(readxl)
ea8e91473dc8 "planemo upload for repository https://forgemia.inra.fr/redelac/redelac-toolbox/-/tree/4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4/tools/REDELACSticsSimulator commit 4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4-dirty"
siwaa
parents:
diff changeset
6
ea8e91473dc8 "planemo upload for repository https://forgemia.inra.fr/redelac/redelac-toolbox/-/tree/4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4/tools/REDELACSticsSimulator commit 4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4-dirty"
siwaa
parents:
diff changeset
7 workspace <- paste0(getwd(), "/WS")
ea8e91473dc8 "planemo upload for repository https://forgemia.inra.fr/redelac/redelac-toolbox/-/tree/4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4/tools/REDELACSticsSimulator commit 4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4-dirty"
siwaa
parents:
diff changeset
8 javastics_path <- getwd()
ea8e91473dc8 "planemo upload for repository https://forgemia.inra.fr/redelac/redelac-toolbox/-/tree/4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4/tools/REDELACSticsSimulator commit 4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4-dirty"
siwaa
parents:
diff changeset
9 default_config_path <- paste0(javastics_path, "/config")
ea8e91473dc8 "planemo upload for repository https://forgemia.inra.fr/redelac/redelac-toolbox/-/tree/4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4/tools/REDELACSticsSimulator commit 4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4-dirty"
siwaa
parents:
diff changeset
10
ea8e91473dc8 "planemo upload for repository https://forgemia.inra.fr/redelac/redelac-toolbox/-/tree/4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4/tools/REDELACSticsSimulator commit 4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4-dirty"
siwaa
parents:
diff changeset
11 txt_path <- paste0(getwd(), "/WS/txt_files")
ea8e91473dc8 "planemo upload for repository https://forgemia.inra.fr/redelac/redelac-toolbox/-/tree/4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4/tools/REDELACSticsSimulator commit 4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4-dirty"
siwaa
parents:
diff changeset
12
ea8e91473dc8 "planemo upload for repository https://forgemia.inra.fr/redelac/redelac-toolbox/-/tree/4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4/tools/REDELACSticsSimulator commit 4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4-dirty"
siwaa
parents:
diff changeset
13 print("==================================")
ea8e91473dc8 "planemo upload for repository https://forgemia.inra.fr/redelac/redelac-toolbox/-/tree/4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4/tools/REDELACSticsSimulator commit 4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4-dirty"
siwaa
parents:
diff changeset
14
ea8e91473dc8 "planemo upload for repository https://forgemia.inra.fr/redelac/redelac-toolbox/-/tree/4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4/tools/REDELACSticsSimulator commit 4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4-dirty"
siwaa
parents:
diff changeset
15 print(paste0("Cores=", detectCores()))
ea8e91473dc8 "planemo upload for repository https://forgemia.inra.fr/redelac/redelac-toolbox/-/tree/4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4/tools/REDELACSticsSimulator commit 4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4-dirty"
siwaa
parents:
diff changeset
16 print(paste0("javastics=", javastics_path))
ea8e91473dc8 "planemo upload for repository https://forgemia.inra.fr/redelac/redelac-toolbox/-/tree/4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4/tools/REDELACSticsSimulator commit 4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4-dirty"
siwaa
parents:
diff changeset
17 print(paste0("ws=", workspace))
ea8e91473dc8 "planemo upload for repository https://forgemia.inra.fr/redelac/redelac-toolbox/-/tree/4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4/tools/REDELACSticsSimulator commit 4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4-dirty"
siwaa
parents:
diff changeset
18 print(paste0("out_dir=", txt_path))
ea8e91473dc8 "planemo upload for repository https://forgemia.inra.fr/redelac/redelac-toolbox/-/tree/4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4/tools/REDELACSticsSimulator commit 4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4-dirty"
siwaa
parents:
diff changeset
19
ea8e91473dc8 "planemo upload for repository https://forgemia.inra.fr/redelac/redelac-toolbox/-/tree/4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4/tools/REDELACSticsSimulator commit 4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4-dirty"
siwaa
parents:
diff changeset
20 print("==================================")
ea8e91473dc8 "planemo upload for repository https://forgemia.inra.fr/redelac/redelac-toolbox/-/tree/4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4/tools/REDELACSticsSimulator commit 4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4-dirty"
siwaa
parents:
diff changeset
21
ea8e91473dc8 "planemo upload for repository https://forgemia.inra.fr/redelac/redelac-toolbox/-/tree/4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4/tools/REDELACSticsSimulator commit 4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4-dirty"
siwaa
parents:
diff changeset
22 # List of successive USMs
ea8e91473dc8 "planemo upload for repository https://forgemia.inra.fr/redelac/redelac-toolbox/-/tree/4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4/tools/REDELACSticsSimulator commit 4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4-dirty"
siwaa
parents:
diff changeset
23 successive_usms_file <- ("successionPlan.csv")
ea8e91473dc8 "planemo upload for repository https://forgemia.inra.fr/redelac/redelac-toolbox/-/tree/4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4/tools/REDELACSticsSimulator commit 4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4-dirty"
siwaa
parents:
diff changeset
24 successive_usms_tab <- read.csv(file = file.path(workspace, successive_usms_file), sep =";")
ea8e91473dc8 "planemo upload for repository https://forgemia.inra.fr/redelac/redelac-toolbox/-/tree/4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4/tools/REDELACSticsSimulator commit 4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4-dirty"
siwaa
parents:
diff changeset
25
3
f262814e48a3 "planemo upload for repository https://forgemia.inra.fr/redelac/redelac-toolbox/-/tree/acafb1f877e923efa13655229681753dfa1928c0/tools/REDELACSticsSimulator commit acafb1f877e923efa13655229681753dfa1928c0-dirty"
siwaa
parents: 2
diff changeset
26 #no_cores <- detectCores() - 1
2
ea8e91473dc8 "planemo upload for repository https://forgemia.inra.fr/redelac/redelac-toolbox/-/tree/4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4/tools/REDELACSticsSimulator commit 4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4-dirty"
siwaa
parents:
diff changeset
27 #no_cores <- 10
3
f262814e48a3 "planemo upload for repository https://forgemia.inra.fr/redelac/redelac-toolbox/-/tree/acafb1f877e923efa13655229681753dfa1928c0/tools/REDELACSticsSimulator commit acafb1f877e923efa13655229681753dfa1928c0-dirty"
siwaa
parents: 2
diff changeset
28 #cl <- makeCluster(no_cores)
f262814e48a3 "planemo upload for repository https://forgemia.inra.fr/redelac/redelac-toolbox/-/tree/acafb1f877e923efa13655229681753dfa1928c0/tools/REDELACSticsSimulator commit acafb1f877e923efa13655229681753dfa1928c0-dirty"
siwaa
parents: 2
diff changeset
29 #registerDoParallel(cl)
2
ea8e91473dc8 "planemo upload for repository https://forgemia.inra.fr/redelac/redelac-toolbox/-/tree/4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4/tools/REDELACSticsSimulator commit 4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4-dirty"
siwaa
parents:
diff changeset
30
3
f262814e48a3 "planemo upload for repository https://forgemia.inra.fr/redelac/redelac-toolbox/-/tree/acafb1f877e923efa13655229681753dfa1928c0/tools/REDELACSticsSimulator commit acafb1f877e923efa13655229681753dfa1928c0-dirty"
siwaa
parents: 2
diff changeset
31 result <- list()
2
ea8e91473dc8 "planemo upload for repository https://forgemia.inra.fr/redelac/redelac-toolbox/-/tree/4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4/tools/REDELACSticsSimulator commit 4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4-dirty"
siwaa
parents:
diff changeset
32
3
f262814e48a3 "planemo upload for repository https://forgemia.inra.fr/redelac/redelac-toolbox/-/tree/acafb1f877e923efa13655229681753dfa1928c0/tools/REDELACSticsSimulator commit acafb1f877e923efa13655229681753dfa1928c0-dirty"
siwaa
parents: 2
diff changeset
33 #result <- foreach(i=1:nrow(successive_usms_tab),
f262814e48a3 "planemo upload for repository https://forgemia.inra.fr/redelac/redelac-toolbox/-/tree/acafb1f877e923efa13655229681753dfa1928c0/tools/REDELACSticsSimulator commit acafb1f877e923efa13655229681753dfa1928c0-dirty"
siwaa
parents: 2
diff changeset
34 # .packages = c("SticsRFiles", "SticsOnR") ) %dopar% {
f262814e48a3 "planemo upload for repository https://forgemia.inra.fr/redelac/redelac-toolbox/-/tree/acafb1f877e923efa13655229681753dfa1928c0/tools/REDELACSticsSimulator commit acafb1f877e923efa13655229681753dfa1928c0-dirty"
siwaa
parents: 2
diff changeset
35 for(i in 1:nrow(successive_usms_tab)) {
2
ea8e91473dc8 "planemo upload for repository https://forgemia.inra.fr/redelac/redelac-toolbox/-/tree/4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4/tools/REDELACSticsSimulator commit 4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4-dirty"
siwaa
parents:
diff changeset
36
ea8e91473dc8 "planemo upload for repository https://forgemia.inra.fr/redelac/redelac-toolbox/-/tree/4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4/tools/REDELACSticsSimulator commit 4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4-dirty"
siwaa
parents:
diff changeset
37 nusms <- as.numeric(successive_usms_tab[i,2])
ea8e91473dc8 "planemo upload for repository https://forgemia.inra.fr/redelac/redelac-toolbox/-/tree/4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4/tools/REDELACSticsSimulator commit 4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4-dirty"
siwaa
parents:
diff changeset
38
ea8e91473dc8 "planemo upload for repository https://forgemia.inra.fr/redelac/redelac-toolbox/-/tree/4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4/tools/REDELACSticsSimulator commit 4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4-dirty"
siwaa
parents:
diff changeset
39 vec <- as.character(successive_usms_tab[i,c(3:(2+nusms))])
ea8e91473dc8 "planemo upload for repository https://forgemia.inra.fr/redelac/redelac-toolbox/-/tree/4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4/tools/REDELACSticsSimulator commit 4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4-dirty"
siwaa
parents:
diff changeset
40
ea8e91473dc8 "planemo upload for repository https://forgemia.inra.fr/redelac/redelac-toolbox/-/tree/4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4/tools/REDELACSticsSimulator commit 4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4-dirty"
siwaa
parents:
diff changeset
41 list_successive_usms <- list(vec)
ea8e91473dc8 "planemo upload for repository https://forgemia.inra.fr/redelac/redelac-toolbox/-/tree/4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4/tools/REDELACSticsSimulator commit 4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4-dirty"
siwaa
parents:
diff changeset
42
ea8e91473dc8 "planemo upload for repository https://forgemia.inra.fr/redelac/redelac-toolbox/-/tree/4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4/tools/REDELACSticsSimulator commit 4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4-dirty"
siwaa
parents:
diff changeset
43 sim_options <- stics_wrapper_options(javastics = javastics_path,
ea8e91473dc8 "planemo upload for repository https://forgemia.inra.fr/redelac/redelac-toolbox/-/tree/4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4/tools/REDELACSticsSimulator commit 4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4-dirty"
siwaa
parents:
diff changeset
44 stics_exe = paste0(javastics_path,"/bin/stics_modulo"),
ea8e91473dc8 "planemo upload for repository https://forgemia.inra.fr/redelac/redelac-toolbox/-/tree/4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4/tools/REDELACSticsSimulator commit 4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4-dirty"
siwaa
parents:
diff changeset
45 workspace = txt_path,
ea8e91473dc8 "planemo upload for repository https://forgemia.inra.fr/redelac/redelac-toolbox/-/tree/4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4/tools/REDELACSticsSimulator commit 4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4-dirty"
siwaa
parents:
diff changeset
46 verbose = TRUE,
ea8e91473dc8 "planemo upload for repository https://forgemia.inra.fr/redelac/redelac-toolbox/-/tree/4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4/tools/REDELACSticsSimulator commit 4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4-dirty"
siwaa
parents:
diff changeset
47 successive = list_successive_usms)
ea8e91473dc8 "planemo upload for repository https://forgemia.inra.fr/redelac/redelac-toolbox/-/tree/4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4/tools/REDELACSticsSimulator commit 4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4-dirty"
siwaa
parents:
diff changeset
48 list_usms <- vec
4
70ae7516e925 "planemo upload for repository https://forgemia.inra.fr/redelac/redelac-toolbox/-/tree/94d9549470e1fe96ae832b04bea58b2f1c5663fc/tools/REDELACSticsSimulator commit 94d9549470e1fe96ae832b04bea58b2f1c5663fc-dirty"
siwaa
parents: 3
diff changeset
49
70ae7516e925 "planemo upload for repository https://forgemia.inra.fr/redelac/redelac-toolbox/-/tree/94d9549470e1fe96ae832b04bea58b2f1c5663fc/tools/REDELACSticsSimulator commit 94d9549470e1fe96ae832b04bea58b2f1c5663fc-dirty"
siwaa
parents: 3
diff changeset
50 singleResult = stics_wrapper(model_options = sim_options, situation = list_usms)
70ae7516e925 "planemo upload for repository https://forgemia.inra.fr/redelac/redelac-toolbox/-/tree/94d9549470e1fe96ae832b04bea58b2f1c5663fc/tools/REDELACSticsSimulator commit 94d9549470e1fe96ae832b04bea58b2f1c5663fc-dirty"
siwaa
parents: 3
diff changeset
51
70ae7516e925 "planemo upload for repository https://forgemia.inra.fr/redelac/redelac-toolbox/-/tree/94d9549470e1fe96ae832b04bea58b2f1c5663fc/tools/REDELACSticsSimulator commit 94d9549470e1fe96ae832b04bea58b2f1c5663fc-dirty"
siwaa
parents: 3
diff changeset
52 result = append(result, list(singleResult))
2
ea8e91473dc8 "planemo upload for repository https://forgemia.inra.fr/redelac/redelac-toolbox/-/tree/4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4/tools/REDELACSticsSimulator commit 4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4-dirty"
siwaa
parents:
diff changeset
53 }
ea8e91473dc8 "planemo upload for repository https://forgemia.inra.fr/redelac/redelac-toolbox/-/tree/4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4/tools/REDELACSticsSimulator commit 4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4-dirty"
siwaa
parents:
diff changeset
54
4
70ae7516e925 "planemo upload for repository https://forgemia.inra.fr/redelac/redelac-toolbox/-/tree/94d9549470e1fe96ae832b04bea58b2f1c5663fc/tools/REDELACSticsSimulator commit 94d9549470e1fe96ae832b04bea58b2f1c5663fc-dirty"
siwaa
parents: 3
diff changeset
55 #stopCluster(cl)
2
ea8e91473dc8 "planemo upload for repository https://forgemia.inra.fr/redelac/redelac-toolbox/-/tree/4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4/tools/REDELACSticsSimulator commit 4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4-dirty"
siwaa
parents:
diff changeset
56
ea8e91473dc8 "planemo upload for repository https://forgemia.inra.fr/redelac/redelac-toolbox/-/tree/4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4/tools/REDELACSticsSimulator commit 4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4-dirty"
siwaa
parents:
diff changeset
57 for (i in 1:nrow(successive_usms_tab)) { #i=1
ea8e91473dc8 "planemo upload for repository https://forgemia.inra.fr/redelac/redelac-toolbox/-/tree/4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4/tools/REDELACSticsSimulator commit 4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4-dirty"
siwaa
parents:
diff changeset
58 if (i == 1) {
ea8e91473dc8 "planemo upload for repository https://forgemia.inra.fr/redelac/redelac-toolbox/-/tree/4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4/tools/REDELACSticsSimulator commit 4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4-dirty"
siwaa
parents:
diff changeset
59 simPCP <- result[[i]]
ea8e91473dc8 "planemo upload for repository https://forgemia.inra.fr/redelac/redelac-toolbox/-/tree/4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4/tools/REDELACSticsSimulator commit 4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4-dirty"
siwaa
parents:
diff changeset
60 } else {
ea8e91473dc8 "planemo upload for repository https://forgemia.inra.fr/redelac/redelac-toolbox/-/tree/4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4/tools/REDELACSticsSimulator commit 4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4-dirty"
siwaa
parents:
diff changeset
61 simPCP$sim_list <- c(simPCP$sim_list, result[[i]]$sim_list)
ea8e91473dc8 "planemo upload for repository https://forgemia.inra.fr/redelac/redelac-toolbox/-/tree/4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4/tools/REDELACSticsSimulator commit 4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4-dirty"
siwaa
parents:
diff changeset
62 }
ea8e91473dc8 "planemo upload for repository https://forgemia.inra.fr/redelac/redelac-toolbox/-/tree/4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4/tools/REDELACSticsSimulator commit 4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4-dirty"
siwaa
parents:
diff changeset
63
ea8e91473dc8 "planemo upload for repository https://forgemia.inra.fr/redelac/redelac-toolbox/-/tree/4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4/tools/REDELACSticsSimulator commit 4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4-dirty"
siwaa
parents:
diff changeset
64 }
ea8e91473dc8 "planemo upload for repository https://forgemia.inra.fr/redelac/redelac-toolbox/-/tree/4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4/tools/REDELACSticsSimulator commit 4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4-dirty"
siwaa
parents:
diff changeset
65
ea8e91473dc8 "planemo upload for repository https://forgemia.inra.fr/redelac/redelac-toolbox/-/tree/4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4/tools/REDELACSticsSimulator commit 4c3e6dc71284e3eecf1cfa8402aaf12dc49c1ee4-dirty"
siwaa
parents:
diff changeset
66 save(simPCP, file = "results.RData")